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LPC47N217N 56-Pin Super I/O with LPC Interface
PRODUCT FEATURES
3.3 Volt Operation (5V tolerant) Programmable Wakeup Event Interface (IO_PME# Pin) SMI Support (IO_SMI# Pin) GPIOs (13) Two IRQ Input Pins XNOR Chain PC2001 ACPI 2.0 Compliant 56-pin QFN Lead-free RoHS Compliant package Intelligent Auto Power Management Serial Port
-- One Full Function Serial Port -- High Speed 16C550A Compatible UART with Send/Receive 16-Byte FIFO -- Supports 230k and 460k Baud -- Programmable Baud Rate Generator -- Modem Control Circuitry -- Multiple Base I/O Address options and 15 IRQ Options
Data Brief Multi-Mode Parallel Port with ChiProtectTM
-- Standard Mode IBM PC/XT(R), PC/AT(R), and PS/2TM Compatible Bidirectional Parallel Port -- Enhanced Parallel Port (EPP) Compatible - EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant) -- IEEE 1284 Compliant Enhanced Capabilities Port (ECP) -- ChiProtect Circuitry for Protection Against Damage Due to Printer Power-On -- 192 Base I/O Address, 15 IRQ and 3 DMA Options -- -- -- -- -- Multiplexed Command, Address and Data Bus 8-Bit I/O Transfers 8-Bit DMA Transfers 16-Bit Address Qualification Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems -- PCI CLKRUN# Support -- Power Management Event (IO_PME#) Interface Pin
LPC Bus Host Interface
SMSC LPC47N217N 56QFN
PRODUCT PREVIEW
Revision 0.3 (09-16-09)
56-Pin Super I/O with LPC Interface
ORDER NUMBER(S): LPC47N217N-ABZJ for 56-pin QFN Lead-free ROHS Compliant package LPC47N217N-ABZJ-TR for 56-pin QFN Lead-free ROHS Compliant package (tape and reel)
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright (c) 2009 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Revision 0.3 (09-16-09)
PRODUCT PREVIEW
2
SMSC LPC47N217N 56QFN
56-Pin Super I/O with LPC Interface
General Description
The SMSC LPC47N217N is a 3.3V PC 99, PC2001, and ACPI 2.0 compliant Super I/O Controller. The LPC47N217N implements the LPC interface, a pin reduced ISA interface which provides the same or better performance as the ISA/X-bus with a substantial savings in pins used. The part also includes 13 GPIO pins. The LPC47N217N incorporates a 16C550A compatible UART and one Multi-Mode parallel port with ChiProtectTM circuitry plus EPP and ECP support. The LPC47N217N is easy to use and offers lower system cost and reduced board area. The LPC47N217N offers a full 16-bit internally decoded address bus, a Serial IRQ interface with PCI CLKRUN# support, relocatable configuration ports, and three DMA channel options. The parallel port is compatible with IBM PC/AT architectures, as well as IEEE 1284 EPP and ECP. The parallel port ChiProtectTM circuitry prevents damage caused by an attached powered printer when the LPC47N217N is not powered. The LPC47N217N features Software Configurable Logic (SCL) for ease of use. SCL allows programmable system configuration of key functions such as the parallel port and UART. The LPC47N217N supports the ISA Plug-and-Play Standard register set (Version 1.0a) and provides the recommended functionality to support Windows operating systems, PC99, and PC2001. The I/O Address, DMA Channel, and Hardware IRQ of each device in the LPC47N217N may be reprogrammed through the internal configuration registers. There are multiple I/O address location options, a Serialized IRQ interface, and three DMA channels.
SMSC LPC47N217N 56QFN
PRODUCT PREVIEW
3
Revision 0.3 (09-16-09)
56-Pin Super I/O with LPC Interface
Block Diagram
PD[0:7], IO_SMI#* IO_PME# MULTI-MODE PARALLEL PORT BUSY, SLCT, PE, nERROR, nACK nSLCTIN, nALF nINIT, nSTROBE
SMI PME WDT
CONTROL, ADDRESS, DATA
GENERAL PURPOSE I/O
GP10, GP11, GP12*, GP13*, GP14*, GP23, GP4[1:7]
SER_IRQ PCI_CLK LAD0 LAD1 LAD2 LAD3 LFRAME# LDRQ# PCI_RESET# LPCPD# CLKRUN#
SERIAL IRQ
CONFIGURATION REGISTERS
ACPI BLOCK
IRQIN1*, IRQIN2*
TXD1, nRTS1, nDTR1 LPC BUS INTERFACE 16C550 COMPATIBLE SERIAL PORT 1
nCTS1, RXD1, nDSR1, nDCD1, nRI1
CLOCK GEN
V TR Vcc GND
CLOCKI
* Denotes Multifunction Pins
Figure 1 LPC47N217N Block Diagram
Revision 0.3 (09-16-09)
PRODUCT PREVIEW
4
SMSC LPC47N217N 56QFN
56-Pin Super I/O with LPC Interface
Package Outline
REVISION HISTORY
REVISION DESCRIPTION INITIAL RELEASE REMOVE "PRELIMINARY" NOTE L(MAX) FROM 0.55 TO 0.50. ADDED D2/E2 VARIATIONS TABLE DATE 2/07/04 10/7/04 7/2/05 RELEASED BY S.K.ILIEV S.K.ILIEV S.K.ILIEV
D D1 e
D2 TERMINAL #1 IDENTIFIER AREA (D/2 X E/2) 3
A B C
3 TERMINAL #1 IDENTIFIER AREA (D1/2 X E1/2) E1 E E2 2
EXPOSED PAD
56X L
4X 45X0.6 MAX (OPTIONAL)
56X b 2
TOP VIEW
BOTTOM VIEW
A A1
A2
SIDE VIEW
D2 / E2 VARIATIONS CATALOG PART
NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETER. 2. POSITION TOLERANCE OF EACH TERMINAL AND EXPOSED PAD IS 0.05mm AT MAXIMUM MATERIAL CONDITION. DIMENSIONS "b" APPLIES TO PLATED TERMINALS AND IT IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM THE TERMINAL TIP. 3. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WITHIN THE AREA INDICATED.
UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN MILLIMETERS AND TOLERANCES ARE: DECIMAL X.X 0.1 X.XX 0.05 X.XXX 0.025 ANGULAR 1
THIRD ANGLE PROJECTION
80 ARKAY DRIVE HAUPPAUGE, NY 11788 USA
TITLE
DIM AND TOL PER ASME Y14.5M - 1994
MATERIAL
NAME
DRAWN
DATE
3-D VIEWS
FINISH
-
S.K.ILIEV
CHECKED
2/06/04 2/07/04
PACKAGE OUTLINE 56 TERMINAL QFN, 8x8mm BODY, 0.5mm PITCH
DWG NUMBER
S.K.ILIEV
APPROVED
MO-56-QFN-8x8
STD COMPLIANCE SHEET
REV
C 1 OF 1
PRINT WITH "SCALE TO FIT" DO NOT SCALE DRAWING
SCALE
S.K.ILIEV
2/07/04
1:1
JEDEC: MO-220
Figure 2 LPC47N217N 56-Pin QFN Package, 8x8mm Body, 0.5mm Pitch
SMSC LPC47N217N 56QFN
PRODUCT PREVIEW
5
Revision 0.3 (09-16-09)

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